A RISC-V hardware platform can contain one or more RISC-V-compatible processing cores to gether with other non-RISC-V-compatible cores, fixed-function accelerators, various physical mem ory structures, I/O devices, and an interconnect structure to allow the components to communicate.
A component is termed a core if it contains an independent instruction fetch unit. A RISC-V compatible core might support multiple RISC-V-compatible hardware threads, or harts, through multithreading.
A RISC-V core might have additional specialized instruction-set extensions or an added coprocessor. We use the term coprocessor to refer to a unit that is attached to a RISC-V core and is mostly sequenced by a RISC-V instruction stream, but which contains additional architectural state and instruction-set extensions, and possibly some limited autonomy relative to the primary RISC-V instruction stream.
We use the term accelerator to refer to either a non-programmable fixed-function unit or a core that can operate autonomously but is specialized for certain tasks. In RISC-V systems, we expect many programmable accelerators will be RISC-V-based cores with specialized instruction-set extensions and/or customized co processors. An important class of RISC-V accelerators are I/O accelerators, which offload I/O processing tasks from the main application cores.
The system-level organization of a RISC-V hardware platform can range from a single-core micro controller to a many-thousand-node cluster of shared-memory manycore server nodes. Even small systems-on-a-chip might be structured as a hierarchy of multicomputers and/or multiprocessors to modularization development effort or to provide secure isolation between subsystems.