Risc-V Processor

The main features of FII-IPcore :

1. Fully supports the RV32IMFAC instruction architecture and provides a rich set of storage and interfaces, including: ITCM 64K(Instruction Tightly Coupled Memories) and DTCM 64K(Data Tightly Coupled Memories) for separate storage of instructions and data, and 2M bytes External super RAM support as well .
2. 3-stage pipeline architecture
3. support machine mode only
4. From instruction fetch ,Decoder ,Execution to memory operation modules are 100% Manually developed by using pure verilog HDL, scalable and easy to be understood.
5.  The flexible RISC-V IPCORE is suitable for customized ASIC for specific domain, Also can be used as embedded CPU with in FPGA.
6.  Interrupt controller, supports 16 high-priority, low-latency local vectored interrupts.
7. includes a RISC-V standard PLIC (platform-level interrupt controller ), which supports 127 global interrupts with 7 priority levels. provides the standard RISCV machine-mode timer and software interrupts via the CLINT(Core Local Interruptor)
8. 2 UART
9. 3 QSPI
10. I2C
11. 3 PWM
12. 10M/100M/1G ethernet
13. Watchdog
14. 32 GPIO
15. 4 7-seg display interface
16. External Serial Flash
17. Debug Interfaces: JTAG
18. 12-Bit ADC
19. Four data lines I2S and can support maximum of 8 audio outputs or 4 stereo channels
20. Hardware Crypto Engine for Advanced Fast Security, Including: AES 128, CRC, Checksum etc

A lot of our Risc-V experiments and our Risc-V courses are based on our own FII-CPU on our FII-PRX100 platform:

• C Programming (2) on RISCV FII-PRX100 (ARTIX-7, XC7A100T) XILINX FPGA Board with our FII-Risc-V CPU (RV32G2.0)
• C Programming (1) on RISCV FII-PRX100 (ARTIX-7, XC7A100T) XILINX FPGA Board with our FII-Risc-V CPU (RV32G2.0)
• Risc-V Bus and PipeLine – FII Risc-V Bus and Pipeline Design – Risc-V Tutorial and Exercise
• FII RISC-V3.01 CPU Processor on FII-PRX100-S (ARTIX-7, XC7A100T) XILINX FPGA Board Evaluation by Coremark and Dhrystone Benchmarks
• Dhrystone Porting Guide For FII RISC-V3.01 CPU Processor on FII-PRX100-S (ARTIX-7, XC7A100T) XILINX FPGA Board
• FII RISC-V3.01 CPU Processor on FII-PRX100-S (ARTIX-7, XC7A100T) XILINX FPGA Board Coremark Porting Guide
• RISC-V Instruction Set Explanation

Codasip is proud to be a founding member of the RISC-V Foundation, joining industry leaders such as Google, Oracle, HP, AMD, Nvidia, and many others.

The power of RISC-V board is that it defines an ISA that helps a healthy HW and SW ecosystems develop, allowing each vendor to deliver their own unique value.

Cloud server will use Risc-V Processor in the near future. If you want to have a cheap cloud hosting with no downtime, please go to PowerHoster.